1. Field of the Invention
The present invention relates to an automatic clock signal phase adjusting circuit for use with a digital magnetic recording and reproducing apparatus adopting a partial response class IV coding method, the circuit adjusting the phase of a reproduced clock signal automatically.
2. Description of the Related Art
FIG. 7 is a block diagram of a prior art digital magnetic recording and reproducing apparatus adopting a partial response class IV coding method, and FIGS. 8(a) through 8(f2) are timing charts depicting the timings of signals or data used by the apparatus of FIG. 7. The timings (a) through (f2) shown in FIG. 8 correspond respectively to data or signals "a" through "f" included in FIG. 7.
In FIG. 7, a coding circuit, not shown, codes an analog video signal into coded data "a." The coded data "a" enter an input terminal 1 of a pre-coder comprising a modulo-two adder 2 and one-bit delay circuits 3 and 4. The pre-coder performs on the data "a" a partial response class IV pre-coding operation whose transfer function is 1/(1-D.sup.2) for conversion to a recording code "b." The recording code "b" is supplied through a recording amplifier 5 to a recording head 6 for recording onto a magnetic tape 7.
The recording code "b" is reproduced via a reproducing head 8 and a reproducing amplifier 9. The recording head 6, magnetic tape 7 and reproducing head 8 constitute an electromagnetic conversion system whose transfer function is (1-D).
A signal from the reproducing amplifier 9 is sent through an equalizer 10 to an adder 11. The adder 11 is also fed with a signal "c" from the equalizer 10 via a one-bit delay circuit 12. The adder 11 and one-bit delay circuit 12 provide the encoding of transfer function (1+D). The pre-coder, the electromagnetic conversion system and the arrangement made of the adder 11 and one-bit delay circuit 12 combine to provide the operation: EQU 1/(1-D.sup.2).times.(1-D).times.(1+D)=1
This effects the transmission of transfer function =1 and generates a ternary signal "d" pursuant to the partial response class IV coding.
The ternary signal "d" is supplied to a ternary decision circuit 13. When the signal level is between L1 (e.g., 0.5) and L2 (e.g., -0.5), the ternary decision circuit 13 recognizes 0; when the signal level is higher than L1 or lower than L2, the ternary decision circuit 13 recognizes 1. This allows the coded data in effect before pre-coding (indicated by "f") to be restored.
The recording code restored by the ternary decision circuit 13 is sent from an output terminal 14 to a decoding circuit, not shown. The decoding circuit decodes what it has received into an analog video signal.
The output signal "c" of the equalizer 10 is also fed to a PLL circuit 15 whereby a clock signal is reproduced. The reproduced clock signal is sent to a phase adjusting circuit 16 for phase adjustment. The phase adjusting circuit 16 outputs a clock signal "e" with its phase adjusted. The clock signal "e" is supplied from an output terminal 17 to various circuits as their operation clock signal.
Suppose that the clock signal "e" takes the form of (e1). In that case, the ternary decision circuit 13 samples the center portion of each bit in the ternary signal "d." As a result, the output signal "f" is a signal reconstituting the coded data "a" precisely, as shown in (f1) of FIG. 8 (f1). If the clock signal lags in phase, as indicated in FIG. 8 (e2), the ternary decision circuit 13 samples the peripheral portion of each bit in the ternary signal "d." This results in an output signal "f" containing an error, as indicated in FIG. 8 (f2). (The sixth bit from left is the error in FIG. 8 (f2)).
For these reasons, the decoded analog video signal is conventionally observed on a monitor, not shown. With the signal being monitored, the amount of phase shift produced by the phase adjusting circuit 16 is adjusted manually so that the error rate of the signal is minimized.
Manual adjustment of the clock signal phase on the conventional digital magnetic recording and reproducing apparatus involves a number of disadvantages. One such disadvantage is the need to adjust the phase frequently whenever the clock signal goes out of phase due to temperature changes. Another disadvantage is that the differences in characteristic between magnetic tapes entail a shifted phase of the clock signal reproduced by the PLL circuit from a different magnetic tape. This requires manually adjusting the phase of the clock signal every time a magnetic tape of different characteristics is reproduced.